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Intel(R) Pentium(R) 4 Processor in the 423-pin Package at 1.30 GHz, 1.40 GHz, 1.50 GHz, 1.60 GHz, 1.70 GHz and 1.80 GHz
Datasheet
Product Features
s Available
at 1.30, 1.40,1.50, 1.60, 1.70 and 1.80 GHz s Binary compatible with applications running on previous members of the Intel microprocessor line (R) s Intel NetBurstTM micro-architecture s System bus frequency at 400 MHz s Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency s Hyper Pipelined Technology s Advance Dynamic Execution -- Very deep out-of-order execution -- Enhanced branch prediction s Level 1 Execution Trace Cache stores 12K micro-ops and removes decoder latency from main execution loops
s8
KB Level 1 data cache KB Advanced Transfer Cache (on-die, full speed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC) s 144 new Streaming SIMD Extensions 2 (SSE2) instructions s Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance s Power Management capabilities -- System Management mode -- Multiple low-power states s Optimized for 32-bit applications running on advanced 32-bit operating systems s 8-way cache associativity provides improved cache hit rate on reads/store operations.
s 256
The Intel(R) Pentium(R) 4 processor is designed for high-performance desktops and entry level workstations. It is binary compatible with previous Intel Architecture processors. The Pentium 4 processor provides great performance for applications running on advanced operating systems such as Windows* 98, Windows ME, Windows 2000 and UNIX*. This is achieved by the Intel(R) NetBurstTM micro-architecture which brings a new level of performance for system buyers. The Pentium 4 processor extends the power of the Pentium III processor with performance headroom for advanced audio and video internet capabilities. Systems based on Pentium 4 processors also include the latest features to simplify system management and lower the total cost of ownership for large and small business environments. The Pentium 4 processor offers great performance for today's and tomorrow's applications.
Order Number: 249198-004 July 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) Pentium(R) 4 Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel, Pentium, and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or it subsidiaries in the United States and other countries. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Other brands and names may be claimed as the property of others.
Contents
Contents
1.0 Introduction .................................................................................................................. 7
1.1 1.2 Terminology........................................................................................................... 8 1.1.1 Processor Packaging Terminology........................................................... 8 References ............................................................................................................ 9 System Bus and GTLREF ...................................................................................11 Power and Ground Pins ......................................................................................11 Decoupling Guidelines ........................................................................................11 2.3.1 VCC Decoupling .....................................................................................12 2.3.2 System Bus AGTL+ Decoupling.............................................................12 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................12 Voltage Identification ...........................................................................................12 2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................13 Reserved, Unused Pins, and TESTHI[10:0]........................................................15 System Bus Signal Groups .................................................................................16 Asynchronous GTL+ Signals...............................................................................17 Test Access Port (TAP) Connection....................................................................17 Maximum Ratings................................................................................................18 Processor DC Specifications...............................................................................18 AGTL+ System Bus Specifications .....................................................................21 System Bus AC Specifications ............................................................................22 Processor AC Timing Waveforms .......................................................................25 BCLK Signal Quality Specifications and Measurement Guidelines.....................31 System Bus Signal Quality Specifications and Measurement Guidelines...........32 System Bus Signal Quality Specifications and Measurement Guidelines...........33 3.3.1 Overshoot/Undershoot Guidelines .........................................................33 3.3.2 Overshoot/Undershoot Magnitude .........................................................34 3.3.3 Overshoot/Undershoot Pulse Duration...................................................34 3.3.4 Activity Factor .........................................................................................34 3.3.5 Reading Overshoot/Undershoot Specification Tables............................35 3.3.6 Determining if a System Meets the Over/Undershoot Specifications .....35 Package Load Specifications ..............................................................................46 Processor Insertion Specifications ......................................................................47 Processor Mass Specifications ...........................................................................47 Processor Materials.............................................................................................47 Processor Markings.............................................................................................48 Processor Pin-Out Coordinates...........................................................................48 Processor Pin Assignments ................................................................................51 5.1.1 Pin Listing by Pin Name .........................................................................51 5.1.2 Pin Listing by Pin Number ......................................................................57
2.0
Electrical Specifications........................................................................................11
2.1 2.2 2.3
2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13
3.0
System Bus Signal Quality Specifications ....................................................31
3.1 3.2 3.3
4.0
Package Mechanical Specifications .........................................................................43
4.1 4.2 4.3 4.4 4.5 4.6
5.0
Pin Listing and Signal Definitions ...........................................................................51
5.1
3
Contents
5.2
Alphabetical Signals Reference .......................................................................... 63 Thermal Specifications........................................................................................ 72 Thermal Analysis................................................................................................. 72 6.2.1 Measurements For Thermal Specifications............................................ 72 6.2.1.1 Processor Case Temperature Measurement ............................ 72 Power-On Configuration Options ........................................................................ 75 Clock Control and Low Power States.................................................................. 75 7.2.1 Normal State--State 1 ........................................................................... 75 7.2.2 AutoHALT Powerdown State--State 2 .................................................. 75 7.2.3 Stop-Grant State--State 3 ..................................................................... 76 7.2.4 HALT/Grant Snoop State--State 4 ........................................................ 77 7.2.5 Sleep State--State 5.............................................................................. 77 7.2.6 Deep Sleep State--State 6 .................................................................... 78 Thermal Monitor .................................................................................................. 78 7.3.1 Thermal Diode........................................................................................ 79 Introduction ......................................................................................................... 81 Mechanical Specifications................................................................................... 81 8.2.1 Boxed Processor Fan Heatsink Dimensions .......................................... 82 8.2.2 Boxed Processor Fan Heatsink Weight.................................................. 83 8.2.3 Boxed Processor Retention Mechanism and Fan Heatsink Supports.... 83 Boxed Processor Requirements ......................................................................... 84 8.3.1 Fan Heatsink Power Supply ................................................................... 84 Thermal Specifications........................................................................................ 85 8.4.1 Boxed Processor Cooling Requirements ............................................... 85 8.4.2 Variable Speed Fan ............................................................................... 87 Logic Analyzer Interface (LAI)............................................................................ 89 9.1.1 Mechanical Considerations .................................................................... 89 9.1.2 Electrical Considerations........................................................................ 89
6.0
Thermal Specifications and Design Considerations................................. 71
6.1 6.2
7.0
Features ....................................................................................................................... 75
7.1 7.2
7.3
8.0
Boxed Processor Specifications ................................................................................ 81
8.1 8.2
8.3 8.4
9.0
Debug Tools Specifications........................................................................................ 89
9.1
4
Contents
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................14 Phase Lock Loop (PLL) Filter Requirements ......................................................15 AC Test Circuit ....................................................................................................26 TCK Clock Waveform..........................................................................................26 Differential Clock Waveform................................................................................27 System Bus Common Clock Valid Delay Timings...............................................27 System Bus Reset and Configuration Timings....................................................28 Source Synchronous 2X (Address) Timings .......................................................28 Source Synchronous 4X Timings ........................................................................29 Power-On Reset and Configuration Timings.......................................................29 Test Reset Timings .............................................................................................30 BCLK[1:0] Signal Integrity Waveform..................................................................32 Low-to-High System Bus Receiver Ringback Tolerance.....................................33 High-to-Low System Bus Receiver Ringback Tolerance.....................................33 Maximum Acceptable Overshoot/Undershoot Waveform ...................................41 Exploded View of Processor Components on a System Board ..........................43 Processor Package .............................................................................................44 Processor Cross-Section and Keep-in ................................................................45 Processor Pin Detail............................................................................................46 IHS Flatness Specification ..................................................................................46 Processor Markings.............................................................................................48 Processor Pinout Diagram - Bottom View ...........................................................49 Example Thermal Solution (Not to scale)............................................................71 Guideline Locations for Case Temperature (TCASE) Thermocouple Placement73 Technique for Measuring with 0 Degree Angle Attachment ................................73 Technique for Measuring with 90 Degree Angle Attachment ..............................73 Stop Clock State Machine ...................................................................................76 Mechanical Representation of the Boxed Pentium 4 Processor .........................81 Side View Space Requirements for the Boxed Processor ..................................82 Top View Space Requirements for the Boxed Processor ...................................83 Boxed Processor Fan Heatsink Power Cable Connector Description.................84 Acceptable System Board Power Header Placement Relative to Processor Socket ..............................................................................85 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view).86 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view).86 Boxed Processor Fan Heatsink Set Points .........................................................87
5
Contents
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 References............................................................................................................ 9 Voltage Identification Definition........................................................................... 13 System Bus Pin Groups ...................................................................................... 16 Processor DC Absolute Maximum Ratings ......................................................... 18 Voltage and Current Specifications..................................................................... 19 System Bus Differential BCLK Specifications ..................................................... 20 AGTL+ Signal Group DC Specifications ............................................................. 20 Asynchronous GTL+ and TAP Signal Group DC Specifications ......................... 21 AGTL+ Bus Voltage Definitions........................................................................... 21 System Bus Differential Clock Specifications...................................................... 22 System Bus Common Clock AC Specifications .................................................. 22 System Bus Source Synch AC Specifications AGTL+ Signal Group .................. 23 Asynchronous GTL+ Signals AC Specifications ................................................. 24 System Bus AC Specifications (Reset Conditions) ............................................. 24 TAP Signals AC Specifications ........................................................................... 25 BCLK Signal Quality Specifications .................................................................... 31 Ringback Specifications for AGTL+, Asynchronous GTL+, and TAP Signal Groups ...................................................................................... 32 Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors) ......................................... 37 Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors) ......................................... 37 Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors) ......................................... 38 Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.7V Processors) ......................................... 38 Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors) ........................................................................... 39 Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors) ............................................................................ 39 Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors) ............................................................................ 40 Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.75V Processors) ............................................................................ 40 Description Table for Processor Dimensions ...................................................... 45 Package Dynamic and Static Load Specifications .............................................. 47 Processor Mass .................................................................................................. 47 Processor Material Properties............................................................................. 48 Pin Listing by Pin Name ...................................................................................... 51 Pin Listing by Pin Number................................................................................... 57 Signal Description ............................................................................................... 63 Processor Thermal Design Power ..................................................................... 72 Power-On Configuration Option Pins .................................................................. 75 Thermal Diode Parameters ................................................................................. 79 Thermal Diode Interface...................................................................................... 80 Fan Heatsink Power and Signal Specifications................................................... 84 Boxed Processor Fan Heatsink Set Points ......................................................... 87
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
1.0
Introduction
The Intel(R) Pentium(R) 4 Processor in the 423-pin Package socket with Intel(R) NetBurst microarchitechture is based on a new 32-bit micro-architecture that operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of IA-32 processors. While based on the Intel(R) NetBurst micro-architecture, it still maintains the tradition of compatibility with IA-32 software. The Intel NetBurst micro-architecture features include hyper pipelined technology, a rapid execution engine, a 400 MHz system bus, and an execution trace cache. The hyper pipelined technology doubles the pipeline depth in the Pentium 4 processor, allowing the processor to reach much higher core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in 1/2 clock tick. The 400 MHz system bus is a quadpumped bus running off a 100 MHz system clock making 3.2 GB/sec data transfer rates possible. The execution trace cache is a level 1 cache that stores approximately 12k decoded microoperations, which removes the decoder from the main execution path, thereby increasing performance. Improved features within the Intel NetBurst micro-architecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 256kB, on-die level 2 cache with increased bandwidth over previous micro-architectures. The floating point and multimedia units have been improved by making the registers 128 bits wide and adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for double-precision floating point, SIMD integer, and memory management. The Streaming SIMD Extensions 2 enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. The Pentium 4 processor supports uni-processor configurations only. As a result of this integration, the return to Pin Grid Array (PGA) style processor packaging is possible. The same manageability features which are included in Intel(R) Pentium(R) III processors are included on Pentium 4 processors with the addition of Thermal Monitor. The Thermal Monitor allows systems to be designed for anticipated processor thermals as opposed to worst case with no performance degradation expected. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep have also been retained for power management capabilities. New heat sinks, heat sink retention mechanisms, and sockets are required for the Pentium 4 processor in the 423-pin package. The socket for the Pentium 4 processor in the 423-pin package is called the 423-Pin Socket in this and other documentation. Through-hole ZIF technology will be used for the 423-Pin Socket. Reference heat sink and retention mechanism designs have been developed with manufacturability as a high priority. Hence, mechanical assembly can be completed from the top of the motherboard and should not require any special tooling. The Pentium 4 processor in the 423-pin package uses a new scalable system bus protocol referred to as the "system bus" in this document. The Pentium 4 processor system bus utilizes a splittransaction, deferred reply protocol similar to that of the P6 processor family system bus, but is not compatible with the P6 processor family system bus. The system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance. Whereas the P6 processor family transfers data once per bus clock, the Pentium 4 processor transfers data four times per bus clock
7
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
(4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a `double-clocked' or 2X address bus. In addition, the Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 Gbytes/second (3200Mbytes/sec). Finally, the system bus also introduces transactions that are used to deliver interrupts. Signals on the system bus use Assisted GTL+ (AGTL+) level voltages which are fully described in the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide.
1.1
Terminology
A `#' symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the `#' symbol implies that the signal is inverted. For example, D[3:0] = `HLHL' refers to a hex `A', and D[3:0]# = `LHLH' also refers to a hex `A' (H= High logic level, L= Low logic level). "System bus" refers to the interface between the processor and system core logic (a.k.a. the chipset components). The system bus is a interface to the processor, memory, and I/O. For this document, "system bus" is used as the generic term for the Pentium 4 processor bus.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
* Intel(R) Pentium(R) 4 Processor in the 423-pin Package--The entire product including
processor core, integrated heat spreader, and interposer.
* Pentium 4 processor--Throughout this document "Pentium 4 processor" refers to the Intel(R)
Pentium(R) 4 Processor in the 423-pin Package.
* Interposer --The structure on which the processor core package and I/O pins are mounted. * Processor core --The processor's execution engine. All AC timings and signal integrity
specifications are to the silicon of the processor core.
* Integrated heat spreader --The surface used to make contact between a heatsink or other
thermal solution and the processor. Abbreviated as IHS.
* 423-Pin Socket --The connector which mates the Pentium 4 processor to the system board. * Retention mechanism --The support structure that is mounted on the system board to
provide added support and retention for heatsinks.
* OLGA (Organic Land Grid Array) Package --Microprocessor packaging using "flip chip"
design, where the processor is attached to the substrate face-down for better signal integrity, more efficient heat removal and lower inductance.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
1.2
References
Material and concepts available in the following documents may be beneficial when reading this document:
Table 1.
References
Document Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide AP-485, Intel Processor Identification and the CPUID Instruction Intel(R) Intel(R) Pentium(R) Pentium(R) 4 Processor Thermal Design Guidelines 4 Processor EMI Guidelines 241618 Order Number1
Voltage Regulator Module (VRM) 9.0 DC-DC Converter Design Guidelines 423-Pin Socket (PGA423) Design Guidelines Intel Architecture Software Developer's Manual Volume I: Basic Architecture Volume II: Instruction Set Reference Volume III: System Programming Guide Intel(R) Intel(R) Pentium(R) Pentium(R) 4 Processor I/O Buffer Models2 243193 243190 243191 243192
4 Processor Overshoot Checker Tool2
Note: 1. Contact your Intel representative for the latest revision of the documents without order numbers. 2. The I/O Buffer Models are in IBIS format.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
10
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
2.0
2.1
Electrical Specifications
System Bus and GTLREF
Most system bus signals of the Intel(R) Pentium(R) 4 Processor in the 423-pin Package system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the Intel P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Unlike the P6 processor family, the termination voltage level for the Pentium 4 processor AGTL+ signals is VCC, the operating voltage of the processor core. P6 family processors utilize a fixed 1.5V termination voltage known as VTT. Because of the speed improvements to data and address busses, signal integrity and platform design methods become more critical than with previous processor families. Design guidelines for the Pentium 4 processor system bus are detailed in the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide. The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board (See Table 13 for GTLREF specifications). Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ signals. Some AGTL+ signals do not include on-die termination and must be terminated on the system board. See Table 4 for details regarding these signals. The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. Contact your Intel Field Representative to obtain the buffer models, Intel(R) Pentium(R) 4 Processor I/O Buffer Models.
2.2
Power and Ground Pins
For clean on-chip power distribution, Pentium 4 processors have 111 VCC (power) and 112 VSS (ground) inputs. All power pins must be connected to VCC, while all VSS pins must be connected to a system ground plane.The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
2.3
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
2.3.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator (or VRM pins) to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (VRM). For more details on this topic, refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide.
2.3.2
System Bus AGTL+ Decoupling
Pentium 4 processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. For more information, refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide.
2.3.3
System Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the processor. As in previous generation processors, the Pentium 4 processor core frequency is a multiple of the BCLK[1:0] frequency. The Pentium 4 processor bus ratio multiplier is set at its default ratio at manufacturing. No jumpers or user intervention is necessary, the processor will automatically run at the speed indicated on the package. Unlike previous processors, the Pentium 4 processor uses a differential clocking implementation. For more information on Pentium 4 processor clocking, refer to the CK00 Clock Synthesizer/Driver Design Guidelines.
2.4
Voltage Identification
The VID specification for Pentium 4 processors is different from that of previous generations and is supported by the VRM 9.0 DC-DC Convertor Design Guidelines. The voltage set by the VID pins is the maximum voltage allowed by the processor. A minimum voltage is provided in Table 5 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification. The specifications have been set such that one voltage regulator can work with all supported frequencies. Pentium 4 processors use five voltage identification pins, VID[4:0], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[4:0]. A `1' in this table refers to an open pin and a `0' refers to low voltage level. The definition provided in Table 2 is not related in any way to previous processors or VRMs. If the processor socket is empty (VID[4:0] = 11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. See the VRM 9.0 DC/DC Converter Design Guidelines for more details. Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 2.
Voltage Identification Definition
Processor Pins VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCC_MAX VRM output off 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
2.4.1
Phase Lock Loop (PLL) Power and Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Pentium 4 processor silicon. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC. A typical filter topology is shown in Figure 1. The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or CIO in Figure 1), is as follows:
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
* * * *
< 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements) > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide. Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution
VCC R
L VCCA CA PLL Processor Core
VSSA CIO R VCCIOPLL L
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
.
Figure 2. Phase Lock Loop (PLL) Filter Requirements
0.2 dB 0 dB -0.5 dB forbidden zone
-28 dB
forbidden zone
-34 dB
DC passband
1 Hz
fpeak
1 MHz
66 MHz
fcore
high frequency band
NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
2.5
Reserved, Unused Pins, and TESTHI[10:0]
All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Pentium 4 processors. See Chapter 5.0 for a pin listing of the processor and the location of all RESERVED pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. In a system level design, on-die termination has been included on the Pentium 4 processor to allow signals to be terminated within the processor silicon. Most unused AGTL+ inputs should be left as no connects, as AGTL+ termination is provided on the processor silicon. However, see Table 3 for details on AGTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value for the on-die termination resistors (RTT). See Table 9.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Therefore, the system board must properly terminate these signals. Signal termination for these signal types is discussed in the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide. The TESTHI[10:0] pins must be connected to VCC via a pull-up resistor. TESTHI[10:0] may be connected individually to VCC via pull-up resistors between 1 k and 10 k value. Alternately, TESTHI[1:0] may be tied together and pulled up to VCC with a single 1 k - 4.7 k resistor; TESTHI[7:2] may be tied together and pulled up to VCC with a single 1 k - 4.7 k resistor; and TESTHI[10:8] may be tied together and pulled up to VCC with a single 1 k - 4.7 k resistor. However, tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing.
2.6
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 3 identifies which signals are common clock, source synchronous, and asynchronous.
Table 3.
System Bus Pin Groups (Page 1 of 2)
Signal Group AGTL+ Common Clock Input Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY# AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#
AGTL+ Common Clock I/O
Signals REQ[4:0]#, A[16:3]#5 AGTL+ Source Synchronous I/O Synchronous to assoc. strobe A[35:17]#
5
Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
AGTL+ Strobes
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 3.
System Bus Pin Groups (Page 2 of 2)
Signal Group Asynchronous GTL+ Input4 Asynchronous GTL+ Output4 TAP Input4 TAP Output4 System Bus Clock Power/Other Synchronous to TCK Synchronous to TCK Clock Type Signals1 A20M#, DBR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, IERR#, THERMTRIP#, PROCHOT# TCK, TDI, TMS, TRST# DBR3, TDO BCLK[1:0], ITP_CLK[1:0]3 VCC, VCCA, VCCIOPLL, VID[4:0], VSS, VSSA, GTLREF[3:0], COMP[1:0], RESERVED, SKTOCC#, TESTHI[10:0], THERMDA, THERMDC, VCC_SENSE, VSS_SENSE
NOTE: 1. Refer to Section 5.2 for signal descriptions. 2. These AGTL+ signals do not have on-die termination and must be terminated on the system board. 3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 4. These signal groups are not terminated by the processor. They must be terminated on the system board. 5. The value of these pins during the active-to-inactive edge of RESET# determine processor configuration options. See Section 7.1 for details.
2.7
Asynchronous GTL+ Signals
Pentium 4 processors do not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) utilize GTL+ output buffers. All of these signals follow the same DC requirements as AGTL+ signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them. See Section 2.10 and Section 2.12 for the DC and AC specifications for the Asynchronous GTL+ signal groups. See section Section 7.2 for additional timing requirements for entering and leaving the low power states.
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Pentium 4 processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required, with each driving a different voltage level. Refer to Chapter 9.0 for more detailed information.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
2.9
Maximum Ratings
Table 4 lists the processor's maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields.
Table 4.
Processor DC Absolute Maximum Ratings
Symbol TSTORAGE VCC VinAGTL+ VinAsynch_GTL+ IVID Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS Asynch GTL+ buffer DC input voltage with respect to VSS Max VID pin current Min -40 -0.5 -0.3 Max 85 2.1 2.1 Unit C V V 1 Notes
-0.3
2.1 5
V mA
NOTE: 1. This rating applies to any processor pin.
2.10
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core silicon and not the package pins unless noted otherwise. See Chapter 5.0 for the pin signal definitions and signal pin assignments. Most of the signals on the processor system bus are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 7. Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The DC specifications for these signal groups are listed in Table 8. Table 5 through Table 8 list the DC specifications for the Pentium 4 processor and are valid only while meeting specifications for case temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 5.
Voltage and Current Specifications
Symbol VCC VID = 1.7V Parameter VCC for processor at 1.30 GHz 1.40 GHz 1.50 GHz VCC for processor at 1.30 GHz VCC VID = 1.75V 1.40 GHz 1.50 GHz 1.60 GHz 1.70 GHz 1.80 GHz VCC_MID VCC for processor at maximum current ICC for processor ICC VID = 1.70V 1.30 GHz 1.40 GHz 1.50 GHz ICC for processor 1.30 GHz ICC VID = 1.75V 1.40 GHz 1.50 GHz 1.60 GHz 1.70 GHz 1.80 GHz ICC Stop-Grant, ICC Sleep 1.30 GHz ISGNT ISLP 1.40 GHz 1.50 GHz 1.60 GHz 1.70 GHz 1.80 GHz IDSLP ITCC ICC_PLL ICC Deep Sleep ICC TCC active ICC for PLL pins 9.7 9.8 9.9 10.7 10.9 11.1 8.7 ICC 30 A A A A A A A A mA 8 7 39.8 42.2 45.0 47.7 50.2 52.7 A A A A A A 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 6, 8 38.1 40.6 43.0 A A A 4, 5, 9 4, 5, 9 4, 5, 9 1.605 1.600 1.595 1.590 1.580 1.575 (VCC_MAX+VCC_MIN)/2 1.75 1.75 1.75 1.75 1.75 1.75 V V V V V V V 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 4 1.565 1.560 1.555 1.70 1.70 1.70 V V V 2, 3, 4, 9 2, 3, 4, 9 2, 3, 4, 9 Min Typ Max Unit Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or early empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 and Table 2 for more information. 3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with a 100MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 4. The processor should not be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MID + 0.055*(1 - ICC/ICC_MAX) [V]. Moreover, Vcc should never exceed VCC_MAX (VID). Failure to adhere to this specification can shorten the processor lifetime.
19
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
5. Maximum current is defined at VCC_MID. 6. The current specified is also for AutoHALT State. 7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor. 8. ICC Stop-Grant, ICC Sleep, and ICC Deep Sleep are specified at VCC_MAX. 9. These specifications apply to "1.7V" processors, i.e., those with a VID = `00110'. 10.These specifications apply to "1.75V" processors, i.e., those with a VID = `00100'.
Table 6.
System Bus Differential BCLK Specifications
Symbol VL VH VCROSS VOV VUS VRBM VTH Parameter Input Low Voltage Input High Voltage Crossing Voltage Overshoot Undershoot Ringback Margin Threshold Region 0.660 0.45*(VH-VL) N/A N/A 0.200 VCROSS -0.100 VCROSS+0.100 Min Typ 0 0.710 0.5*(VH-VL) N/A N/A 0.850 0.55*(VH-VL) 0.3 0.3 Max Unit V V V V V V V Figure 5 5 5 5 5 5 5 2, 3 4 5 6 7 Notes1
NOTES:. 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. The VL and VH used to calculate VCROSS are the actual VL and VH seen by the processor. 4. Overshoot is defined as the absolute value of the maximum voltage allowed above the VH level. 5. Undershoot is defined as the absolute value of the maximum voltage allowed below the VSS level. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region centered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis.
Table 7.
AGTL+ Signal Group DC Specifications
Symbol VIL VIH VOH IOL ILI ILO RON Parameter Input Low Voltage Input High Voltage Output High Voltage Output Low Current Input Leakage Current Output Leakage Current Buffer On Resistance 5 Min -0.150 GTLREF + 100mV GTLREF + 100mV Max GTLREF - 100mV VCC VCC VCC / (0.5*Rtt_min + RON_MIN) 100 100 11 Unit V V V mA A A 5 Notes1 2, 6 3, 4, 6 4, 6 6
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Chapter 4.0. 5. Refer to processor I/O Buffer Models for I/V characteristics.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
6. The VCC referred to in these specifications is the instantaneous VCC.
Table 8.
Asynchronous GTL+ and TAP Signal Group DC Specifications
Symbol VIL VIL VIH VIH VOH IOL ILI ILO Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output High Voltage Output Low Current Input Leakage Current Output Leakage Current Min -0.150 -0.150 GTLREF + 100mV VCC/2 + 0.30 Max GTLREF - 100mV VCC/2 - 0.30 VCC VCC VCC 56 100 100 V mA A A 3, 4, 5 6 V 4, 5 Unit V Notes1 5
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Parameter will be measured at 9mA (for use with system inputs). 3. All outputs are open-drain. 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Chapter 4.0. 5. The VCC referred to in these specifications is the instantaneous VCC. 6. These specifications apply to the asynchronous GTL+ signal group. 7. These specifications apply to the TAP signal group.
2.11
AGTL+ System Bus Specifications
Routing topology recommendations may be found in the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide. Termination resistors are not required for most AGTL+ signals, as these are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal's voltage with a reference voltage called GTLREF (known as VREF in previous documentation). Table 9 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. It is important that the system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on platform design see the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide.
Table 9.
AGTL+ Bus Voltage Definitions
Symbol GTLREF RTT COMP[1:0] Parameter Bus Reference Voltage Termination Resistance COMP Resistance Min -2% 36 42.77 Typ 2/3 VCC 41 43.2 Max +2% 46 45.45 Units V Notes1 2, 3, 6 4 5, 7
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of VCC. 3. GTLREF should be generated from VCC by a voltage divider of 1% resistors or 1% matched resistors. Refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide for implementation details.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O buffer models for I/V characteristics. 5. COMP resistance must be provided on the system board with 1% resistors. See the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide for implementation details. 6. The VCC referred to in these specifications is the instantaneous VCC. 7. A COMP Resistance of 43.2 +/- 1% is the preferred value.
2.12
System Bus AC Specifications
The processor System bus timings specified in this section are defined at the processor core silicon and are thus not measurable at the processor pins. See Chapter 5.0 for the Pentium 4 processor pin signal definitions. Table 10 through Table 15 list the AC specifications associated with the processor system bus. All AGTL+ timings are referenced to GTLREF for both `0' and `1' logic levels unless otherwise specified. The timings specified in this section should be used in conjunction with the I/O buffer models provided by Intel. These I/O buffer models, which include package information, are available for the Pentium 4 processor in IBIS format. AGTL+ layout guidelines are also available in the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guidelines. Care should be taken to read all notes associated with a particular timing parameter.
Table 10. System Bus Differential Clock Specifications
T# Parameter System Bus Frequency T1: BCLK[1:0] Period T2: BCLK[1:0] Period Stability T3: BCLK[1:0] High Time T4: BCLK[1:0] Low Time T5: BCLK[1:0] Rise Time T6: BCLK[1:0] Fall Time 3.94 3.94 175 175 5 5 10.0 Min Nom Max 100 10.2 200 6.12 6.12 700 700 Unit MHz ns ps ns ns ps ps 5 5 5 5 5 5 5 2 3, 4 Figure Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies. 2. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2). 3. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines. 4. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 5. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).
.
Table 11. System Bus Common Clock AC Specifications
T# Parameter T10: Common Clock Output Valid Delay T11: Common Clock Input Setup Time T12: Common Clock Input Hold Time T13: RESET# Pulse Width Min 0.20 0.65 0.40 1.00 10.00 Max 1.45 Unit ns ns ns ms Figure 6 6 6 7 Notes1,2,3 4 5 5 6, 7, 8
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core. 4. Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF at 2/3 VCC 2%. 5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.4 V/ ns to 4.0V/ns. 6. RESET# can be asserted asynchronously, but must be deasserted synchronously. 7. This should be measured after VCC and BCLK[1:0] become stable. 8. Maximum specification applies only while PWRGOOD is asserted.
.
Table 12. System Bus Source Synch AC Specifications AGTL+ Signal Group
T# Parameter T20: Source Synchronous Data Output Valid Delay (first data/address only) T21: TVBD: Source Synchronous Data Output Valid Before Strobe T22: TVAD: Source Synchronous Data Output Valid After Strobe T23: TVBA: Source Synchronous Address Output Valid Before Strobe T24: TVAA: Source Synchronous Address Output Valid After Strobe T25: TSUSS: Source Synchronous Input Setup Time to Strobe T26: THSS: Source Synchronous Input Hold Time to Strobe T27: TSUCC: Source Synchronous Input Setup Time to BCLK[1:0] T28: TFASS: First Address Strobe to Second Address Strobe T29: TFDSS: First Data Strobe to Subsequent Strobes T30: Data Strobe `n' (DSTBN#) Output Valid Delay T31: Address Strobe Output Valid Delay 8.80 2.27 Min 0.20 0.85 0.85 1.88 1.88 0.21 0.21 0.65 1/2 n/4 10.20 4.23 Typ Max 1.30 Unit ns ns ns ns ns ns ns ns BCLK BCLK ns ns Figure 8, 9 9 9 8 8 8, 9 8, 9 8, 9 8 9 9 8 Notes1,2,3,4 5 5, 8 5, 8 5, 8 5, 9 6 6 7 10 11, 12 13
NOTE: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. Not 100% tested. Specified by design characterization. 3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core. 4. Unless otherwise noted these specifications apply to both data and address timings. 5. Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF at 2/3 VCC 2%. 6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.3 V/ns to 4.0V/ns. 7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide for more information on the definitions and use of these specifications. 9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide for more information on the definitions and use of these specifications. 10.The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of ADSTB#. 11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively. 12.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK period (5 ns) after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#. 13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
Table 13. Asynchronous GTL+ Signals AC Specifications
T# Parameter T35: Asynch GTL+ Input Pulse Width, except PWRGOOD T36: PWRGOOD to RESET# de-assertion time T37: PWRGOOD Inactive Pulse Width T38: PROCHOT# pulse width Min 2 1 10 500 10 Max Unit BCLKs ms BCLKs us 10 10 11 4 5 Figure Notes1,2,3,6
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All Asynch GTL+ signal timings are referenced at GTLREF. 3. These signals may be driven asynchronously. 4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal. 5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion and before the deassertion of PROCHOT# for the processor to complete current instruction execution. 6. See section Section 7.2 for additional timing requirements for entering and leaving the low power states.
Table 14. System Bus AC Specifications (Reset Conditions)
T# Parameter T45: Reset Configuration Signals (A[31:3]#, BR0#, INIT#, SMI#) Setup Time T46: Reset Configuration Signals (A[31:3]#, BR0#, INIT#, SMI#) Hold Time NOTES: 1. Before the deassertion of RESET#. 2. After clock that deasserts RESET#. 3. After the assertion of RESET#. Min 4 2 20 Max Unit BCLKs BCLKs Figure 7 7 1 2 Notes
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 15. TAP Signals AC Specifications
Parameter T55: TCK Period T56: TCK Rise Time T57: TCK Fall Time T58: TMS Rise Time T59: TMS Fall Time T60: TMS Clock to Output Delay T61: TDI Setup Time T62: TDI Hold Time T63: TDO Clock to Output Delay T64: TRST# Assert Time -5 0 3 0.5 2 3.5 Min 60.0 Max 1000 9.5 9.5 8.5 8.5 -2 Unit ns ns ns ns ns ns ns ns ns TCK 11 Figure 4 4 4 4 4 4 4 4 4 5 5, 8 5, 8 6 7 Notes1,2,3
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3. All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at GTLREF at the processor pins. 4. Rise and fall times are measured from the 20% to 80% points of the signal swing. 5. Referenced to the falling edge of TCK. 6. Referenced to the rising edge of FBO (TCK) at the debug port connector. 7. TRST# is synchronized to TCK and is asserted for 5 TCK periods while TMS is asserted. 8. Specification for a minimum swing defined between TAP VIL_MAX to VIH_MIN. This assumes a minimum edge rate of 0.5V/ns.
2.13
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 10 through Table 15. Note: For Figure 4 through Figure 11, the following apply: 1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core. 2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor silicon. 3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+ strobe signal timings are referenced at GTLREF at the processor silicon. 4. All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at the processor pins. The circuit used to test the AC specifications is shown in Figure 3.
25
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 3. AC Test Circuit
VCC VCC 600 mils, 42 ohms, 169 ps/in 2.4nH 1.2pF
AC Timings test measurements made here.
Rload
Rload = 50 ohms
Figure 4. TCK Clock Waveform
80% 20% 50%
tr = T56, T58 (Rise Time) tf = T57, T59 (Fall Time) tp = T55 (TCK Period)
26
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
.
Figure 5. Differential Clock Waveform
Tph Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tpl Tp
Tp = T1 (BCLK[1:0] period) T2 = BCLK[1:0] Period stability (not shown) Tph =T3 (BCLK[1:0] pulse high time) Tpl = T4 (BCLK[1:0] pulse low time) T5 = BCLK[1:0] rise time through the threshold region (not shown) T6 = BCLK[1:0] fall time through the threshold region (not shown)
Figure 6. System Bus Common Clock Valid Delay Timings
T0 BCLK1 BCLK0
TP
T1
T2
Common Clock Signal (@ driver) Common Clock Signal (@ receiver)
valid TQ valid
TP = T10: TCO (Data Valid Output Delay) TQ = T11: TSU (Common Clock Setup) TR = T12: TH (Common Clock Hold Time)
valid TR
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 7. System Bus Reset and Configuration Timings
BCLK
BCLK[1:0]1
Tt
Tu
RESET# Tv Configuration (A20M#, IGNNE#, LINT[1:0]) Configuration (A[14:5]#, BR0#, (A[31:3], BR0#, FLUSH#, INT#) INIT#, SMI#) Tt Tu Tv Tw Tx Ty Safe Tw Valid = T9 (GTL+ Input Hold Time) = T8 (GTL+ Input Setup Time) = T10 (RESET# Pulse Width) = = T13 (RESET# Pulse Signals TvT16 (Reset Configuration Width) (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) Tw = T45 (Reset Configuration Signals Setup Time) T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) Tx = T46 (Reset Configuration Signals Hold Time) Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time) Tz = T18 (Reset Configuration Signals (A20M# IGNNE# LINT[1:0]) Setup Time) Tz Valid Tx
Figure 8. Source Synchronous 2X (Address) Timings
T1
2.5 ns 5.0 ns 7.5 ns
T2
BCLK1 BCLK0 ADSTB# (@ driver)
TP TR TH valid TS TJ TH valid TJ
A# (@ driver)
ADSTB# (@ receiver)
TK
A# (@ receiver)
valid TN TM
valid
TH = T23: Source Sync. Address Output Valid Before Address Strobe TJ = T24: Source Sync. Address Output Valid After Address Strobe TK = T27: Source Sync. Input Setup to BCLK TM = T26: Source Sync. Input Hold Time TN = T25: Source Sync. Input Setup Time TP = T28: First Address Strobe to Second Address Strobe TS = T20: Source Sync. Output Valid Delay TR = T31: Address Strobe Output Valid Delay
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 9. Source Synchronous 4X Timings
T0
2.5 ns 5.0 ns 7.5 ns
T1
T2
BCLK1 BCLK0 DSTBp# (@ driver)
TH
DSTBn# (@ driver)
TA TB TA TD
D# (@ driver)
TJ
DSTBp# (@ receiver)
DSTBn# (@ receiver)
TC
D# (@ receiver)
TE TG TE TG
TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync. Setup Time to BCLK TD = T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay TE = T25: Source Sync. Input Setup Time TG = T26: Source Sync. Input Hold Time TH = T29: First Data Strobe to Subsequent Strobes TJ = T20: Source Sync. Data Output Valid Delay
Figure 10. Power-On Reset and Configuration Timings
BCLK
VCC, Vcc core, VREF PWRGOOD Ta RESET# Tb
Configuration (A20M#, IGNNE#, LINT[1:0])
Tc Valid Ratio
Ta T T37 (PWRGOOD Inactive Pulse Width) = = T15 (PWRGOOD Inactive Pulse Width) Tb Ta T36 (PWRGOOD to RESET# de-assertion time) = = T10 (RESET# Pulse Width) b Tc Tc T46 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) = = T20 (Reset Configuration Signals Hold Time)
29
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 11. Test Reset Timings
TRST# 1.25V GTLREF Tq Tq = T37 (TRST# Pulse Width)
Tq = T64, T38 (TRST# Pulse Width, PROCHOT# Pulse Width)
PCB-773
30
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
3.0
Package Mechanical Specifications
The Intel(R) Pentium(R) 4 Processor in the 423-pin Package uses Pin Grid Array (PGA) package technology. Components of the package include an integrated heat spreader, processor silicon, silicon mounting substrate or Organic Land Grid Array (OLGA), and an interposer which is the pincarrier. Mechanical specifications for the processor are given in this section. See Section 1.1 for a terminology listing. The processor socket which accepts the Pentium 4 processor in the 423-pin package is referred to as a 423-Pin Socket. See the 423-Pin Socket (PGA423) Design Guidelines for further details on the 423-Pin Socket.
Note:
The drawing below is not to scale and is for reference only. The socket and system board are supplied as a reference only.
Figure 12. Exploded View of Processor Components on a System Board
IHS Die OLGA Interposer Socket System board Thermal Interface Capacitors
31
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 13. Processor Package
Pin A1
32
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 16. Description Table for Processor Dimensions
Code Letter A B C D E F G H J K L M N P T U V 0.891 0.727 0.571 0.677 0.055 0.891 Min 2.094 1.217 1.059 0.054 0.509 0.459 0.167 0.941 0.941 Typ 2.100 1.220 1.063 0.079 0.515 0.465 0.192 0.950 0.950 0.100 0.737 0.576 0.687 0.067 0.900 0.100 0.900 0.909 0.747 0.581 0.697 0.079 0.909 3 Max 2.106 1.224 1.067 0.104 0.521 0.471 0.217 0.959 0.959 2 Notes1
NOTES: 1. All dimensions in inches unless otherwise noted. 2. Nickel plated copper. 3. Diameter
Figure 14 details the keep in specification for pin-side components. Pentium 4 processors may contain pin side capacitors mounted to the processor OLGA package. The capacitors will be exposed within the opening of the interposer cavity. Figure 16 details the flatness and tilt specifications for the IHS. Tilt is measured with the reference datum set to the bottom of the processor interposer.
Figure 14. Processor Cross-Section and Keep-in
IHS OLGA Interposer 0.050" .528" Component Keepin Socket must allow clearance for pin shoulders and mate flush with this surface
33
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 15. Processor Pin Detail
1. All dimensions in inches. 2. 8 microinches Au over 80 microinches Ni, min. 3. .010 Diametric true position, pin to pin.
Figure 16. IHS Flatness Specification
3.1
Package Load Specifications
Table 17 provides dynamic and static load specifications for the Pentium 4 processor in the 423-pin package IHS. These mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach solutions
34
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heat sink-to-processor thermal interface. It is not recommended to use any portion of the processor interposer as a mechanical reference or load bearing surface for thermal solutions.
Table 17. Package Dynamic and Static Load Specifications
Parameter Static Dynamic Max 25 100 Unit lbf lbf Notes 1, 2, 3 1, 3, 4
NOTES: 1. This specification applies to a uniform load. 2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface. 3. These parameters are based on design characterization and not tested. 4. Dynamic load specifications are defined assuming a maximum duration of 11ms.
3.2
Processor Insertion Specifications
The Pentium 4 processor in the 423-pin package can be inserted and removed 30 times from a 423pin socket meeting the 423-Pin Socket Design Guidelines document. Note that this specification is based on design characterization and is not tested.
3.3
Processor Mass Specifications
Table 18 specifies the processor's mass. This includes all components which make up the entire processor product.
Table 18. Processor Mass
Processor Pentium 4 processor, 31mm OLGA Mass (grams) 23
3.4
Processor Materials
The Pentium 4 processor is assembled from several components. The basic material properties are described in Table 19.
35
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 19. Processor Material Properties
Component Integrated Heat Spreader Interposer Interposer pins Material Nickel over copper FR4 Gold over nickel Notes
3.5
Processor Markings
The following section details the processor top-side laser markings and is provided to aid in the identification of the Pentium 4 processor. Specific details regarding individual fields in the product markings will be provided in a future release of the EMTS.
Figure 17. Processor Markings
Frequency/Cache/Bus/Voltage Intel(R) pentium(R)bbb 2-D Matrix Mark S-Spec/Country of Assy
1.5GHz/256/400/1.7V SYYYY XXXXXX SL4SH MALAY 1234567 FFFFFFFF-NNNN -1272 8 i m c `00
FPO - Serial #
NOTES: 1. Character size for laser markings is: height 0.050", width 0.032". 2. All characters will be in upper case.
3.6
Processor Pin-Out Coordinates
Figure 18 details the coordinates of the 423 processor pins as viewed from the bottom of the package.
36
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 18. Processor Pinout Diagram - Bottom View
39 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW
D[29]# D[21]# VSS D[23]# D[20]# VCC D[4]# D[9]# VSS D[14]# GTLR EF0 VCC VSS_ SENS E A20M# THER MTRIP # VSS GTLR EF2 VSS VCC VSS VCC VSS VSS A[18]#
38
37
36
35
34
33
32
31
30
29
28
27
A[15]#
26
25
A[13]#
24
23
A[14]#
22
21
A[22]#
20
19
A[30]#
18
17
A[20]#
16
15
A[26]#
14
13
A[27]#
12
11
A[33]#
10
9
A[32]#
8
7
6
5
SKTO CC#
4
3
VID3
2
1
VID4
A B
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VID2
VID1
A[12]#
A[10]#
A[29] #
A[23]#
A[21]#
A[34]#
BPM[4 ]#
A[31]#
RSP#
IERR#
STPC LK# BPM[5 ]#
VCC
VID0
C D
A[19]#
A[16]#
A[25]#
BR[1]#
BR[2]#
BR[3]#
AP[1]#
A[35]#
MCER R#
INIT#
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
BPM[3 ]# BPM[0 ]#
VCC
VSS
VCC
E F
A[9]#
COMP [1] ADST B[0]#
A[24]#
A[28]#
BINIT#
AP[0]#
GTLR EF3
BPM[1 ]#
BPM[2 ]#
VSS
VCC
VSS
VSS
ADST B[1]#
VCC
VSS
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
G H
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
J K
VSS
VCC
VSS
VCC
VSS
VCC
VSS
L M
VCC
VSS
VCC
VSS
VCC
VSS
VCC
N P
VSS
VCC
VSS
VCC
VSS
VCC
VSS
R T
VCC
VSS
VCC
RS[2]#
VSS
VCC
VSS
VCC
U V
VCC
VSS
VCC
VSS
BOTTOM VIEW
VCC
VSS
VCC
VSS
W Y
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
AA AB
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
AC AD
D[11]#
D[1]#
VSS
VCC
VSS
VCC
D[3]#
VCC
VSS
VCC
VSS
VCC
AE AF
D[7]#
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
AG AH
VSS
D[12]#
VSS
VCC
VSS
VCC
D[13]#
VSS
VCC
VSS
VCC
AJ AK
D[17]#
D[24]#
VCC
VSS
VCC
VSS
D[31]#
VSS
VCC
VSS
VCC
VSS
AL AM
VCC
VSS
VCC
VSS
VCC
VSS
D[27]#
VSS
VCC
VSS
VCC
AN AP
VCC
D[22]#
D[18]#
D[43]#
D[35]#
D[41]#
D[61]#
D[63]#
GTLR EF1
BCLK[ 1]# BCLK[ 0]#
VSS
VCC
VSS
D[25]#
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
AR AT AU AV AW
D[26]#
D[16]#
D[30]#
D[33]#
D[39]#
D[45]#
D[49]#
D[53]#
D[55]#
D[57]#
D[60]#
VCC
DINV[ 1]#
D[28]#
D[36]#
D[38]#
D[34]#
D[47]#
D[50]#
D[48]#
D[54]#
D[56]#
D[59]#
VCCA
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSSA
D[19]#
DP[1]#
DP[0]#
D[32]#
D[37]#
DP[2]#
D[44]#
D[46]#
D[51]#
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
38
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
4.0
System Bus Signal Quality Specifications
Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines or cause incorrect latching of data. Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and undershoot can cause timing degradation due to the build up of intersymbol interference (ISI) effects. For these reasons, it is crucial that the designer work towards a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing. This section documents signal quality metrics used to derive topology and routing guidelines through simulation, and all specifications are at the processor silicon and cannot be measured at the processor pins. The Intel(R) Pentium(R) 4 Processor Overshoot Checker Tool is to be utilized to determine pass/fail signal quality conditions found through simulation analysis with the Intel(R) Pentium(R) 4 Processor I/O Buffer Models (IBIS format). This tool takes into account the specifications contained in this section. Specifications for signal quality are for measurements at the processor core only and are only observable through simulation. The same is true for all system bus AC timing specifications in Section 2.12. Therefore, proper simulation of the Pentium 4 processor system bus is the only means to verify proper timing and signal quality metrics, and Intel highly recommends simulation during system design and measurement during system analysis.
4.1
BCLK Signal Quality Specifications and Measurement Guidelines
Table 20 describes the signal quality specifications for the processor system bus clock (BCLK) signals. Figure 19 describes the signal quality waveform for the system bus clock at the processor silicon. Specifications are measured at the processor silicon, not the 423-pin Socket pins.
Table 20. BCLK Signal Quality Specifications
Parameter BCLK[1:0] Overshoot BCLK[1:0] Undershoot BCLK[1:0] Ringback Margin BCLK[1:0] Threshold Region Min N/A N/A 0.20 N/A Max 0.30 0.30 N/A 0.10 Unit V V V V Figure 19 19 19 19 2 Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Pentium 4 processor frequencies. 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value.
39
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 19. BCLK[1:0] Signal Integrity Waveform
Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot
4.2
System Bus Signal Quality Specifications and Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide. Table 21 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor silicon. Signal quality measurements cannot be made at the processor pins. The Pentium 4 processor maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 22 through Table 25. Figure 20 shows the system bus ringback tolerance for low-to-high transitions and Figure 21 shows ringback tolerance for high-tolow transitions.
Table 21. Ringback Specifications for AGTL+, Asynchronous GTL+, and TAP Signal Groups
Signal Group All Signals All Signals Transition 01 10 Maximum Ringback (with Input Diodes Present) GTLREF + 0.100 GTLREF - 0.100 Unit V V Figure 20 21 Notes 1,2,3,4,5,6,7 1,2,3,4,5,6,7
NOTES: 1. All signal integrity specifications are measured at the processor silicon. 2. Unless otherwise noted, all specifications in this table apply to all Pentium 4 processor frequencies. 3. Specifications are for the edge rate of 0.3 - 4.0V/ns. 4. All values specified by design characterization. 5. Please see Section 4.3 for maximum allowable overshoot. 6. Ringback between GTLREF + 100 mV and GTLREF - 100 mV is not supported. 7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other sources of system noise.
40
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 20. Low-to-High System Bus Receiver Ringback Tolerance
VCC
+100 mV GTLREF -100 mV
Noise Margin
VSS
Figure 21. High-to-Low System Bus Receiver Ringback Tolerance
VCC
+100 mV GTLREF -100 mV
Noise Margin
VSS
4.3
System Bus Signal Quality Specifications and Measurement Guidelines
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The overshoot/undershoot specifications limit transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (AF) of the incident waveform. Permanent damage to the processor is the likely result of excessive overshoot/undershoot.
4.3.1
41
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be properly modelled. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modelled within Intel I/O buffer models do not clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models are being used to characterize the Pentium 4 processor system bus, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot.
4.3.2
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Pentium 4 processor both overshoot and undershoot are referenced to VSS. It is important to note that overshoot and undershoot conditions are separate and their impacts must be determined independently. Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in Table 22 through Table 25. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications (2.3V for overshoot and -0.65V for undershoot), the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications.
4.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage. The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration. Note 1: Oscillations below the reference voltage cannot be subtracted from the total overshoot/ undershoot pulse duration.
4.3.4
Activity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any common clock signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For source synchronous signals (address, data, and associated strobes), the activity factor is in reference to the strobe edge, since the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. An AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every strobe cycle. The specifications provided in Table 22 through Table 25 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/ undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just
42
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). Note 1: Activity factor for common clock AGTL+ signals is referenced to BCLK[1:0] frequency. Note 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#. Note 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#.
4.3.5
Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the Pentium 4 processor is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the signal group that the particular signal falls into. For AGTL+ signals operating in the 4x source synchronous domain, use Table 22. For AGTL+ signals operating in the 2x source synchronous domain, use Table 23. If the signal is an AGTL+ signal operating in the common clock domain, use Table 24. Finally, all other signals reside in the 33MHz domain (asynchronous GTL+, TAP, etc.) and are referenced in Table 25. 2. Determine the magnitude of the overshoot or the undershoot (relative to VSS). 3. Determine the activity factor (how often does this overshoot occur?). 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive.
4.3.6
Determining if a System Meets the Over/Undershoot Specifications
The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail. A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. Results from simulation may also be evaluated by utilizing the Intel(R) Pentium(R) 4 Processor Overshoot Checker Tool through the use of time-voltage data files. 1. Ensure no signal ever exceeds VCC or -0.25V OR 2. If only one overshoot/undershoot event occurs, ensure it meets the over/undershoot specifications in the following tables OR 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of
43
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where AF=1), then the system passes. The following notes apply to Table 22 through Table 25. NOTES: 1. Absolute Maximum Overshoot magnitude of 2.3V must never be exceeded. 2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative to VCC. 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS. 4. Ringback below VCC can not be subtracted from overshoots/undershoots. 5. Lesser undershoot does not allocate longer or larger overshoot. 6. OEM's are strongly encouraged to follow Intel provided layout guidelines. 7. All values specified by design characterization.
44
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 22. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors)
Absolute Maximum Overshoot (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75 Absolute Maximum Undershoot (V) -0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 Pulse Duration (ns) AF = 1 0.07 0.12 0.23 0.42 0.74 1.38 2.50 4.50 5.00 5.00 5.00 5.00 Pulse Duration (ns) AF = 0.1 0.65 1.22 2.25 4.15 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 Pulse Duration (ns) AF = 0.01 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 Notes 1,2,3,4
NOTES: 1. These specifications are specified at the processor silicon. 2. Assumes a BCLK period of 10 ns. 3. AF is referenced to associated source synchronous strobes. 4. These specifications apply to "1.7V" processors, i.e., those with a VID = `00110'.
Table 23. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors)
Absolute Maximum Overshoot (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75 Absolute Maximum Undershoot (V) -0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 Pulse Duration (ns) AF = 1 0.13 0.24 0.45 0.83 1.48 2.76 5.00 5.00 10.0 10.0 10.0 10.0 Pulse Duration (ns) AF = 0.1 1.30 2.44 4.50 8.30 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 Pulse Duration (ns) AF = 0.01 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 Notes 1,2,3,4
NOTES: 1. These specifications are specified at the processor silicon. 2. Assumes a BCLK period of 10 ns.
45
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
3. AF is referenced to associated source synchronous strobes. 4. These specifications apply to "1.7V" processors, i.e., those with a VID = `00110'.
Table 24. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors)
Absolute Maximum Overshoot (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75 Absolute Maximum Undershoot (V) -0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 Pulse Duration (ns) AF = 1 0.26 0.49 0.90 1.66 2.96 5.52 10.0 18.0 20.0 20.0 20.0 20.0 Pulse Duration (ns) AF = 0.1 2.60 4.88 9.00 16.60 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 Pulse Duration (ns) AF = 0.01 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 Notes 1,2,3,4
NOTES: 1. These specifications are specified at the processor silicon. 2. BCLK period is 10 ns. 3. AF is referenced to BCLK[1:0]. 4. These specifications apply to "1.7V" processors, i.e., those with a VID = `00110'.
Table 25. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.7V Processors)
Absolute Maximum Overshoot (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75 Absolute Maximum Undershoot (V) -0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 Pulse Duration (ns) AF = 1 0.78 1.46 2.70 4.98 8.88 16.56 30.0 54.0 60.0 60.0 60.0 60.0 Pulse Duration (ns) AF = 0.1 7.80 14.64 27.0 49.8 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 Pulse Duration (ns) AF = 0.01 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 Notes 1,2,3
NOTES: 1. These specifications are specified at the processor silicon.
46
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
2. This table assumes a 33MHz time domain. 3. These specifications apply to "1.7V" processors, i.e., those with a VID = `00110'.
Table 26. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors)
Absolute Maximum Overshoot (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 Absolute Maximum Undershoot (V) -0.585 -0.535 -0.485 -0.435 -0.385 -0.335 -0.285 -0.235 -0.185 -0.135 -0.085 Pulse Duration (ns) AF = 1 0.06 0.11 0.22 0.41 0.75 1.35 2.50 4.70 5.00 5.00 5.00 Pulse Duration (ns) AF = 0.1 0.63 1.10 2.20 4.10 5.00 5.00 5.00 5.00 5.00 5.00 5.00 Pulse Duration (ns) AF = 0.01 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 Notes 1,2,3,4
NOTES: 1. These specifications are specified at the processor pad. 2. Assumes a BCLK period of 10 ns. 3. AF is referenced to associated source synchronous strobes. 4. These specifications apply to "1.75V" processors, i.e., those with a VID = `00100'.
Table 27. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors)
Absolute Maximum Overshoot (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 Absolute Maximum Undershoot (V) -0.585 -0.535 -0.485 -0.435 -0.385 -0.335 -0.285 -0.235 -0.185 -0.135 -0.085 Pulse Duration (ns) AF = 1 0.12 0.22 0.44 0.82 1.50 2.70 5.00 9.40 10.0 10.0 10.0 Pulse Duration (ns) AF = 0.1 1.20 2.20 4.40 8.20 10.0 10.0 10.0 10.0 10.0 10.0 10.0 Pulse Duration (ns) AF = 0.01 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 Notes 1,2,3,4
NOTES: 1. These specifications are specified at the processor pad. 2. Assumes a BCLK period of 10 ns.
47
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
3. AF is referenced to associated source synchronous strobes. 4. These specifications apply to "1.75V" processors, i.e., those with a VID = `00100'
Table 28. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors)
Absolute Maximum Overshoot (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 Absolute Maximum Undershoot (V) -0.585 -0.535 -0.485 -0.435 -0.385 -0.335 -0.285 -0.235 -0.185 -0.135 -0.085 Pulse Duration (ns) AF = 1 0.24 0.44 0.88 1.64 3.00 5.40 10.0 18.8 20.0 20.0 20.0 Pulse Duration (ns) AF = 0.1 2.40 4.40 8.80 16.4 20.0 20.0 20.0 20.0 20.0 20.0 20.0 Pulse Duration (ns) AF = 0.01 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 Notes 1,2,3,4
NOTES: 1. These specifications are specified at the processor pad. 2. BCLK period is 10 ns. 3. AF is referenced to associated source synchronous strobes. 4. These specifications apply to "1.75V" processors, i.e., those with a VID = `00100'..
Table 29. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.75V Processors)
Absolute Maximum Overshoot (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 Absolute Maximum Undershoot (V) -0.585 -0.535 -0.485 -0.435 -0.385 -0.335 -0.285 -0.235 -0.185 -0.135 -0.085 Pulse Duration (ns) AF = 1 0.72 1.32 2.64 4.92 9.00 16.2 30.0 56.4 60.0 60.0 60.0 Pulse Duration (ns) AF = 0.1 7.20 13.2 26.4 49.2 60.0 60.0 60.0 60.0 60.0 60.0 60.0 Pulse Duration (ns) AF = 0.01 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 Notes 1,2,3
NOTES: 1. These specifications are specified at the processor pad. 2. This table assumes a 33MHz time domain.
48
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
3. These specifications apply to "1.75V" processors, i.e., those with a VID = `00100'.
Figure 22. Maximum Acceptable Overshoot/Undershoot Waveform
Maximum Absolute Overshoot VMAX VCC
Time-dependent Overshoot
GTLREF VOL VSS VMIN Maximum Absolute Undershoot Time-dependent Undershoot
000588
49
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
50
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
5.0
5.1
Pin Listing and Signal Definitions
Processor Pin Assignments
Section 5.1 contains the pinlist for the Intel(R) Pentium(R) 4 Processor in the 423-pin Package in Table 30 and Table 31. Table 30 is a listing of all processor pins ordered alphabetically by pin name. Table 31 is also a listing of all processor pins but ordered by pin number.
5.1.1
Pin Listing by Pin Name
Table 30. Table 30.
Pin Name A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27#
Pin Listing by Pin Name
Pin Number F20 C21 A19 C11 A9 A11 C15 D12 T38 F36 G25 G21 F16 D14 AR7 AP8 F18 E35 F8 F12 F10 E7 C13 D6 L37 B36 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch GTL+ Common Clock Source Synch Source Synch Common Clock Common Clock Bus Clock Bus Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output
Pin Listing by Pin Name
Pin Number F30 C29 D30 C31 F28 D28 F26 C23 A31 C25 A25 A23 A27 D24 A29 C27 D26 A17 C17 A21 C19 F22 D22 A15 A13 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Pin Name A28# A29# A30# A31# A32# A33# A34# A35# A20M# ADS# ADSTB0# ADSTB1# AP0# AP1# BCLK0 BCLK1 BINIT# BNR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPRI# BR0#
51
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 30.
Pin Name COMP0 COMP1 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36#
Pin Listing by Pin Name
Pin Number AU27 F24 Y38 AD36 W37 AE37 AG39 AA35 V36 AF38 W39 AE39 AB36 AD38 AH36 AJ37 AC37 AA39 AT36 AK38 AP34 AW37 AM38 AU39 AP36 AN39 AK36 AR37 AT38 AN35 AU35 AW39 AT34 AL37 AW31 AT32 AU29 AP26 AU33 Signal Buffer Type Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Table 30.
Pin Name D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# DEFER# DP0# DP1# DP2# DP3# DRDY#
Pin Listing by Pin Name
Pin Number AW29 AU31 AT30 AT28 AP24 AU25 AP28 AW25 AT24 AW23 AU23 AU19 AT20 AU21 AW21 AW19 AT18 AU17 AT16 AU15 AT14 AW13 AU13 AT12 AP14 AW17 AP12 AL39 AU37 AT22 AW15 AV2 B34 J35 AW33 AW35 AW27 AT26 G37 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch GTL+ Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output
52
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 30.
Pin Name DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FERR# GTLREF GTLREF GTLREF GTLREF HIT# HITM# IERR# IGNNE# INIT# ITP_CLK0 ITP_CLK1 LINT0 LINT1 LOCK# MCERR# PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESET# RS0# RS1# RS2# RSP# SKTOCC# SLP#
Pin Listing by Pin Name
Pin Number AG35 AP32 AP22 AP18 AJ35 AP30 AP20 AP16 P38 AC35 AP10 F14 T36 K36 D36 C7 M38 D8 AU1 AW1 H36 W35 A33 D10 F38 AW9 C33 D32 F34 D34 F32 AT4 AW11 M36 N35 U35 C9 A5 AW7 Common Clock Common Clock Common Clock Common Clock Common Clock Power/Other Asynch GTL+ Input Input Input Input Input Output Input Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Common Clock Common Clock Common Clock Asynch GTL+ Asynch GTL+ TAP TAP Asynch GTL+ Asynch GTL+ Common Clock Common Clock Asynch GTL+ Asynch GTL+ Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Output Input Input Input Input Input Input Input/Output Input/Output Output Input Input/Output Input/Output Input/Output Input/Output Input/Output
Table 30.
Pin Name SMI# STPCLK# TCK TDI TDO TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8 TESTHI9 TESTHI10 THERMDA THERMDC
THERMTRIP#
Pin Listing by Pin Name
Pin Number K38 C5 R37 J39 P36 A7 AT10 AT6 AT8 AU7 AU9 AU11 AW5 D16 D18 D20 H38 E39 U37 D38 A35 R35 A37 A39 AA1 AA5 AB38 AB4 AB8 AC3 AC7 AD2 AD6 AE1 AE35 AE5 AF4 AF8 AG3 Signal Buffer Type Asynch GTL+ Asynch GTL+ TAP TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ TAP Common Clock TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Input Input Direction Input Input Input Input Output Input Input Input Input Input Input Input Input Input Input Input
TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
53
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 30.
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Pin Listing by Pin Name
Pin Number AG37 AG7 AH2 AH6 AJ1 AJ39 AJ5 AK4 AK8 AL3 AL7 AM2 AM36 AM6 AN1 AN5 AP38 AP4 AR13 AR17 AR21 AR25 AR29 AR3 AR33 AR9 AT2 AV10 AV14 AV18 AV22 AV26 AV30 AV34 AV38 AV6 B10 B14 B18 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table 30.
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Pin Listing by Pin Name
Pin Number B22 B26 B30 B6 C3 C37 D2 E1 E13 E17 E21 E25 E29 E33 E5 E9 F4 G13 G19 G29 G3 G33 G39 G7 G9 H2 H6 J1 J37 J5 K4 K8 L3 L35 L7 M2 M6 N1 N5 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
54
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 30.
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC_SENSE
Pin Listing by Pin Name
Pin Number P4 P8 R3 R7 T2 T6 U1 U39 U5 V4 V8 W3 W7 Y2 Y36 Y6 N39 AU5 AW3 C1 B2 B4 A3 A1 AA3 AA37 AA7 AB2 AB6 AC1 AC39 AC5 AD4 AD8 AE3 AE7 AF2 AF36 AF6 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Output Direction
Table 30.
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Pin Listing by Pin Name
Pin Number AG1 AG5 AH38 AH4 AH8 AJ3 AJ7 AK2 AK6 AL1 AL35 AL5 AM4 AM8 AN3 AN37 AN7 AP2 AP6 AR1 AR11 AR15 AR19 AR23 AR27 AR31 AR35 AR39 AR5 AU3 AV12 AV16 AV20 AV24 AV28 AV32 AV36 AV8 B12 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
VCCA VCCIOPLL VID0 VID1 VID2 VID3 VID4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
55
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 30.
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Pin Listing by Pin Name
Pin Number B16 B20 B24 B28 B32 B38 B8 C35 C39 D4 E11 E15 E19 E23 E27 E3 E31 E37 F2 F6 G1 G11 G15 G17 G23 G27 G31 G35 G5 H4 H8 J3 J7 K2 K6 L1 L39 L5 M4 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table 30.
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS_SENSE
Pin Listing by Pin Name
Pin Number M8 N3 N37 N7 P2 P6 R1 R5 T4 T8 U3 U7 V2 V38 V6 W1 W5 Y4 Y8 R39 AV4 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Direction
VSSA
56
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
5.1.2
Pin Listing by Pin Number
Table 31 contains a listing of the Pentium 4 processor pins in order by pin number.
Table 31. Pin Listing by Pin Number Table 31. Pin Listing by Pin Number
Pin Number A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 A39 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 Pin Name VID4 VID3 SKTOCC# TESTHI0 A32# A33# A27# A26# A20# A30# A22# A14# A13# A15# A17# A11# LOCK# TRDY# VCC VCC VID1 VID2 VCC VSS VCC VSS VCC VSS VCC VSS VCC Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Direction Output Output Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Pin Number B24 B26 B28 B30 B32 B34 B36 B38 C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 D2 D4 D6 D8 Pin Name VSS VCC VSS VCC VSS DBSY# BR0# VSS VID0 VCC STPCLK# IERR# RSP# A31# BPM4# A34# A21# A23# A29# A10# A12# A18# A4# A6# REQ0# VSS VCC VSS VCC VSS BPM5# INIT# Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Common Clock Power/Other Power/Other Power/Other Asynch GTL+ Common Clock Common Clock Source Synch Common Clock Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Asynch GTL+ Input/Output Input Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input/Output Direction
57
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 31. Pin Listing by Pin Number
Pin Number D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 D38 E1 E3 E5 E7 E9 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E31 E33 E35 E37 E39 F2 F4 F6 F8 Pin Name MCERR# A35# AP1# TESTHI8 TESTHI9 TESTHI10 A25# A16# A19# A8# A5# REQ1# REQ3# HITM# TMS VCC VSS VCC BPM3# VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BNR# VSS THERMDC VSS VCC VSS BPM0# Signal Buffer Type Common Clock Source Synch Common Clock Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock TAP Power/Other Power/Other Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Input/Output Input/Output Direction Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input
Table 31. Pin Listing by Pin Number
Pin Number F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 F32 F34 F36 F38 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 H2 H4 H6 H8 Pin Name BPM2# BPM1# GTLREF AP0# BINIT# A28# A24# COMP1 A9# A7# A3# REQ4# REQ2# ADS# PROCHOT# VSS VCC VSS VCC VCC VSS VCC VSS VSS VCC ADSTB1# VSS ADSTB0# VSS VCC VSS VCC VSS DRDY# VCC VCC VSS VCC VSS Signal Buffer Type Common Clock Common Clock Power/Other Common Clock Common Clock Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Input/Output Direction Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output
58
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 31. Pin Listing by Pin Number
Pin Number H36 H38 J1 J3 J5 J7 J35 J37 J39 K2 K4 K6 K8 K36 K38 L1 L3 L5 L7 L35 L37 L39 M2 M4 M6 M8 M36 M38 N1 N3 N5 N7 N35 N37 N39 P2 P4 P6 P8 Pin Name LINT0 THERMDA VCC VSS VCC VSS DEFER# VCC TDI VSS VCC VSS VCC HIT# SMI# VSS VCC VSS VCC VCC BPRI# VSS VCC VSS VCC VSS RS0# IGNNE# VCC VSS VCC VSS RS1# VSS VCC_SENSE VSS VCC VSS VCC Signal Buffer Type Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other TAP Power/Other Power/Other Power/Other Power/Other Common Clock Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Input Input Input Input/Output Input Input Input Direction Input
Table 31. Pin Listing by Pin Number
Pin Number P36 P38 R1 R3 R5 R7 R35 R37 R39 T2 T4 T6 T8 T36 T38 U1 U3 U5 U7 U35 U37 U39 V2 V4 V6 V8 V36 V38 W1 W3 W5 W7 W35 W37 W39 Y2 Y4 Y6 Y8 Pin Name TDO FERR# VSS VCC VSS VCC TRST# TCK VSS_SENSE VCC VSS VCC VSS GTLREF A20M# VCC VSS VCC VSS RS2# THERMTRIP# VCC VSS VCC VSS VCC D6# VSS VSS VCC VSS VCC LINT1 D2# D8# VCC VSS VCC VSS Signal Buffer Type TAP Asynch GTL+ Power/Other Power/Other Power/Other Power/Other TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Common Clock Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Input Input/Output Input/Output Input/Output Input Output Input Input Input Input Output Direction Output Output
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 31. Pin Listing by Pin Number
Pin Number Y36 Y38 AA1 AA3 AA5 AA7 AA35 AA37 AA39 AB2 AB4 AB6 AB8 AB36 AB38 AC1 AC3 AC5 AC7 AC35 AC37 AC39 AD2 AD4 AD6 AD8 AD36 AD38 AE1 AE3 AE5 AE7 AE35 AE37 AE39 AF2 AF4 AF6 AF8 Pin Name VCC D0# VCC VSS VCC VSS D5# VSS D15# VSS VCC VSS VCC D10# VCC VSS VCC VSS VCC GTLREF D14# VSS VCC VSS VCC VSS D1# D11# VCC VSS VCC VSS VCC D3# D9# VSS VCC VSS VCC Signal Buffer Type Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Direction
Table 31. Pin Listing by Pin Number
Pin Number AF36 AF38 AG1 AG3 AG5 AG7 AG35 AG37 AG39 AH2 AH4 AH6 AH8 AH36 AH38 AJ1 AJ3 AJ5 AJ7 AJ35 AJ37 AJ39 AK2 AK4 AK6 AK8 AK36 AK38 AL1 AL3 AL5 AL7 AL35 AL37 AL39 AM2 AM4 AM6 AM8 Pin Name VSS D7# VSS VCC VSS VCC DSTBN0# VCC D4# VCC VSS VCC VSS D12# VSS VCC VSS VCC VSS DSTBP0# D13# VCC VSS VCC VSS VCC D24# D17# VSS VCC VSS VCC VSS D31# DBI0# VCC VSS VCC VSS Signal Buffer Type Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 31. Pin Listing by Pin Number
Pin Number AM36 AM38 AN1 AN3 AN5 AN7 AN35 AN37 AN39 AP2 AP4 AP6 AP8 AP10 AP12 AP14 AP16 AP18 AP20 AP22 AP24 AP26 AP28 AP30 AP32 AP34 AP36 AP38 AR1 AR3 AR5 AR7 AR9 AR11 AR13 AR15 AR17 AR19 AR21 Pin Name VCC D20# VCC VSS VCC VSS D27# VSS D23# VSS VCC VSS BCLK1 GTLREF D63# D61# DSTBP3# DSTBN3# DSTBP2# DSTBN2# D41# D35# D43# DSTBP1# DSTBN1# D18# D22# VCC VSS VCC VSS BCLK0 VCC VSS VCC VSS VCC VSS VCC Signal Buffer Type Power/Other Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other System Bus Clk Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Bus Clk Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction
Table 31. Pin Listing by Pin Number
Pin Number AR23 AR25 AR27 AR29 AR31 AR33 AR35 AR37 AR39 AT2 AT4 AT6 AT8 AT10 AT12 AT14 AT16 AT18 AT20 AT22 AT24 AT26 AT28 AT30 AT32 AT34 AT36 AT38 AU1 AU3 AU5 AU7 AU9 AU11 AU13 AU15 AU17 AU19 AU21 Pin Name VSS VCC VSS VCC VSS VCC VSS D25# VSS VCC RESERVED TESTHI2 TESTHI3 TESTHI1 D60# D57# D55# D53# D49# DBI2# D45# DP3# D40# D39# D33# D30# D16# D26# ITP_CLK0 VSS VCCA TESTHI4 TESTHI5 TESTHI5 D59# D56# D54# D48# D50# Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch TAP Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Power/Other Input/Output Direction
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 31. Pin Listing by Pin Number
Pin Number AU23 AU25 AU27 AU29 AU31 AU33 AU35 AU37 AU39 AV2 AV4 AV6 AV8 AV10 AV12 AV14 AV16 AV18 AV20 AV22 AV24 AV26 AV28 AV30 AV32 AV34 AV36 AV38 AW1 AW3 AW5 AW7 AW9 AW11 AW13 AW15 AW17 AW19 AW21 Pin Name D47# D42# COMP0 D34# D38# D36# D28# DBI1# D21# DBR# VSSA VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC ITP_CLK1 VCCIOPLL TESTHI7 SLP# PWRGOOD RESET# D58# DBI3# D62# D52# D51# Signal Buffer Type Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Asynch GTL+ Asynch GTL+ Common Clock Source Synch Source Synch Source Synch Source Synch Source Synch Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output
Table 31. Pin Listing by Pin Number
Pin Number AW23 AW25 AW27 AW29 AW31 AW33 AW35 AW37 AW39 Pin Name D46# D44# DP2# D37# D32# DP0# DP1# D19# D29# Signal Buffer Type Source Synch Source Synch Common Clock Source Synch Source Synch Common Clock Common Clock Source Synch Source Synch Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
5.2
Alphabetical Signals Reference
Table 32. Signal Description (Page 1 of 8)
Name Type
36
Description A[35:3]# (Address) define a 2 -byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Pentium 4 processor in the 423pin package system bus. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# pins to determine power-on configuration. See Section 7.1 for more details. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/ write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.
A[35:3]#
Input/ Output
A20M#
Input
ADS#
Input/ Output
ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.
ADSTB[1:0]#
Input/ Output
Signals REQ[4:0]#, A[16:3]# A[35:17]#
Associated Strobe ADSTB0# ADSTB1#
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all Pentium 4 processor system bus agents. The following table defines the coverage model of these signals. AP[1:0]# Input/ Output Request Signals A[35:24]# A[23:3]# REQ[4:0]# subphase 1 AP0# AP1# AP1# subphase 2 AP1# AP0# AP0#
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 32. Signal Description (Page 2 of 8)
Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. Input/ Output If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# activation. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# Input/ Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all Pentium 4 processor system bus agents. Input/ Output BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. Please refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide for more detailed information. These signals do not have on-die termination and must be terminated on the system board. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of all processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this pin is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. COMP[1:0] Analog COMP[1:0] must be terminated on the system board using precision resistors. Refer to Table 9 in Chapter 2.0.
BINIT#
BPM[5:0]#
BPRI#
Input
BR0#
Input/ Output
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 32. Signal Description (Page 3 of 8)
Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#. Quad-Pumped Signal Groups D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DBI# 0 1 2 3
Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DBI[3:0] Assignment To Data Bus DBI[3:0]# Input/ Output Bus Signal DBI3# DBI2# DBI1# DBI0# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]#
DBR#
Output
DBR# is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of all processor system bus agents. DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all Pentium 4 processor system bus agents.
DBSY#
Input/ Output
DEFER#
Input
DP[3:0]#
Input/ Output
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 32. Signal Description (Page 4 of 8)
Name Type Input/ Output Description DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor system bus agents. Data strobe used to latch in D[63:0]#. Signals DSTBN[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobe DSTBN0# DSTBN1# DSTBN2# DSTBN3#
DRDY#
Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobe DSTBP0# DSTBP1# DSTBP2# DSTBP3#
FERR#
Output
FERR# (Floating-point Error) is asserted when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCC. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. Refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide for more information. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. This signal does not have on-die termination and must be terminated on the system board. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.
GTLREF
Input
HIT# HITM#
Input/ Output Input/ Output
IERR#
Output
IGNNE#
Input
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 32. Signal Description (Page 5 of 8)
Name Type Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: Enabled or disabled. MCERR# Input/ Output Asserted, if configured, for internal errors along with IERR#. Asserted, if configured, by the request initiator of a bus transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, please refer to the IA-32 Software Developer's Manual, Volume 3: System Programming Guide. PROCHOT# will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum tested operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. See Section 7.3 for more details.
INIT#
Input
ITP_CLK[1:0]
Input
LINT[1:0]
Input
LOCK#
Input/ Output
PROCHOT#
Output
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 32. Signal Description (Page 6 of 8)
Name Type Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. `Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. Figure 10 illustrates the relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 13, and be followed by a 1 to 10 ms RESET# pulse. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# (Request Command) must connect the appropriate pins of all processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity checking of these signals. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 7.1. This signal does not have on-die termination and must be terminated on the system board. RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this pin to determine if the processor is present. SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If the BCLK input is stopped while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state.
PWRGOOD
Input
REQ[4:0]#
Input/ Output
RESET#
Input
RSP#
Input
SKTOCC#
Output
SLP#
Input
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 32. Signal Description (Page 7 of 8)
Name Type Description SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TESTHI[10:0] must be connected to a VCC power source through 1-10 k resistors for proper processor operation. See Section 2.5 for more details. Thermal Diode Anode. See Section 7.3.1. Thermal Diode Cathode. See Section 7.3.1. The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 135C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched, and the processor stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a RESET# pulse will reset the processor and execution will continue. If the temperature has not dropped below the trip level, the processor will continue to drive THERMTRIP# and remain stopped. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 pull-down resistor. VCCA provides isolated power for the internal processor core PLL's. Refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide for complete implementation details. VCCIOPLL provides isolated power for internal processor system bus PLL's. Follow the guidelines for VCCA, and refer to the Intel(R) Pentium(R) 4 Processor and Intel(R) 850 Chipset Platform Design Guide for complete implementation details. VCCSENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure power near the silicon with little noise.
SMI#
Input
STPCLK#
Input
TCK TDI TDO TESTHI[10:0] THERMDA THERMDC
Input Input Output Input Other Other
THERMTRIP#
Output
TMS
Input
TRDY#
Input
TRST#
Input
VCCA
Input
VCCIOPLL VCCSENSE
Input
Output
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Table 32. Signal Description (Page 8 of 8)
Name Type Description VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage required by the processor. The VID pins are needed to cleanly support processor voltage specification variations. See Table 2 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself. VSSA is the isolated ground for internal PLL's. VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise
VID[4:0]
Output
VSSA VSSSENSE
Input Output
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6.0
Thermal Specifications and Design Considerations
Intel(R) Pentium(R) 4 Processor in the 423-pin Package use an integrated thermal heat spreader for heatsink attachment which is intended to provide for multiple types of thermal solutions. This section will provide data necessary for development of a thermal solution. See Figure 23 for an exploded view of an example Pentium 4 processor thermal solution. This is for illustration purposes only. For further thermal solution design details, please refer to the Intel(R) Pentium(R) 4 Processor Thermal Design Guidelines.
Note:
The processor is either shipped by itself or with a heatsink for boxed processors. See Chapter 8.0 for details on boxed processors.
Figure 23. Example Thermal Solution (Not to scale)
Retention Clip
Heatsink
Processor
Retention Mechanism 423-pin Socket
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
6.1
Thermal Specifications
Table 33 specifies the thermal design power dissipation envelope for Pentium 4 processors. Analysis indicates that real applications are unlikely to cause the processor to consume its maximum possible power consumption. Intel recommends that system thermal designs target the "Thermal Design Power" indicated in Table 33. The Thermal Monitor feature (refer to Section 7.3) is intended to protect the processor from overheating when running high power code that exceeds the recommendations in this table. For more details on the usage of this feature, refer to Section 7.3. In all cases the Thermal Monitor feature must be enabled for the processor to be in specification. Table 33 also lists the maximum and minimum processor temperature specifications for TCASE. A thermal solution should be designed to ensure the temperature of the processor never exceeds these specifications.
Table 33. Processor Thermal Design Power
Processor and Core Frequency (GHz) 1.7V processors 1.30 GHz 1.40 GHz 1.50 GHz 1.75V processors 1.30 GHz 1.40 GHz 1.50 GHz 1.60 GHz 1.70 GHz 1.80 GHz 51.6 54.7 57.8 61.0 64.0 66.7 5 5 5 5 5 5 70 72 73 75 76 78 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 48.9 51.8 54.7 5 5 5 69 70 72 1, 3 1, 3 1, 3 Thermal Design Power (W)2 Minimum TCASE (C) Maximum TCASE (C) Notes
NOTES: 1. These values are specified at VCC_MID for the processor. Systems must be designed to ensure that the processor not be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MID + 0.055*(1 ICC/ICC_MAX) [V] 2. The numbers in this column reflect Intel's recommended design point and are not indicative of the maximum power the processor can dissipate under worst case conditions. For more details refer to the Intel(R) Pentium(R) 4 Processor Thermal Design Guidelines. 3. These specifications apply to "1.7V" processors, i.e., those with a VID = `00110'. 4. These specifications apply to "1.75V" processors, i.e., those with a VID = `00100'.
6.2
6.2.1
6.2.1.1
Thermal Analysis
Measurements For Thermal Specifications
Processor Case Temperature Measurement
The maximum and minimum case temperature (TCASE) for the Pentium 4 processor is specified in Table 33. This temperature specification is meant to ensure correct and reliable operation of the processor. Figure 24 illustrates where Intel recommends that TCASE thermal measurements should be made. Figures 25 and 26 illustrate two possible measuring techniques. Refer to the Intel(R) Pentium(R) 4 Processor Thermal Design Guidelines for more information.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 24. Guideline Locations for Case Temperature (TCASE) Thermocouple Placement
M e asure from ed ge o f processor
1 .125 "
M easure T C A SE a t this point. 1.0 75"
T he rm al grease sh ould cover the entire surfa ce of the Integ ra ted H ea t Sp read er 000 874 b
Figure 25. Technique for Measuring with 0 Degree Angle Attachment
Figure 26. Technique for Measuring with 90 Degree Angle Attachment
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7.0
7.1
Features
Power-On Configuration Options
Several configuration options can be configured by hardware. The Intel(R) Pentium(R) 4 Processor in the 423-pin Package sample its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, please refer to Table 34. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except during another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.
Table 34. Power-On Configuration Option Pins
Configuration Option Output tristate Execute BIST In Order Queue pipelining (set IOQ depth to 1) Disable MCERR# observation Disable BINIT# observation APIC Cluster ID (0-3) Disable bus parking Symmetric agent arbitration ID Pin1 SMI# INIT# A7# A9# A10# A[12:11]# A15# BR0#
NOTE: 1. Asserting this signal during RESET# will select the corresponding option.
7.2
Clock Control and Low Power States
The use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states is allowed in Pentium 4 processor based systems to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 27 for a visual representation of the processor low power states.
7.2.1
Normal State--State 1
This is the normal operating state for the processor.
7.2.2
AutoHALT Powerdown State--State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Power Down state, the processor will process bus snoops.
Figure 27. Stop Clock State Machine
HALT Instruction and HALT Bus Cycle Generated 2. Auto HALT Power Down State BCLK running. Snoops and interrupts allowed. INIT#, BINIT#, INTR, NMI, SMI#, RESET# 1. Normal State Normal execution.
Snoop Event Occurs
Snoop Event Serviced
STP CLK # De
STP CLK # As serte d -ass e rted
STPCLK# Asserted
STPCLK# De-asserted
4. HALT/Grant Snoop State BCLK running. Service snoops to caches.
Snoop Event Occurs Snoop Event Serviced
3. Stop Grant State BCLK running. Snoops and interrupts allowed.
SLP# Asserted
SLP# De-asserted
5. Sleep State BCLK running. No snoops or interrupts allowed. BCLK Input Stopped BCLK Input Restarted
6. Deep Sleep State BCLK stopped. No snoops or interrupts allowed.
7.2.3
Stop-Grant State--State 3
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop Grant state.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK# signal. When re-entering the Stop Grant state from the Sleep state, STPCLK# should only be de-asserted one or more bus clocks after the de-assertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the system bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) will occur with the assertion of the SLP# signal. While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a system bus snoop.
7.2.4
HALT/Grant Snoop State--State 4
The processor will respond to snoop transactions on the system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
7.2.5
Sleep State--State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state. SLP# assertions while the processor is not in the Stop Grant state is out of specification and may result in illegal operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behaviour. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep state, by stopping the BCLK[1:0] inputs. (See Section 7.2.6). Once in the Sleep or Deep Sleep states, the SLP# pin must be de-asserted if another asynchronous system bus event needs to occur. The SLP# pin has a minimum assertion of one BCLK period. When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.
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7.2.6
Deep Sleep State--State 6
Deep Sleep state is the lowest power state the processor can enter while maintaining context. Deep Sleep state is entered by stopping the BCLK[1:0] inputs (after the Sleep state was entered from the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK[1:0] is stopped. To provide maximum power conservation hold the BLCK0 input at VOL and the BCLK1 input at VOH during the Deep Sleep state. Stopping the BCLK input lowers the overall current consumption to leakage levels. To re-enter the Sleep state, the BLCK input must be restarted. A period of 1 ms (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals are allowed on the system bus while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. The processor has to stay in Deep Sleep mode for a minimum of 25 ms. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions.
7.3
Thermal Monitor
Thermal Monitor is a new feature found in the Pentium 4 processor which allows system designers to design lower cost thermal solutions, without compromising system integrity or reliability. By using a factory-tuned, precision on-die thermal sensor, and a fast acting thermal control circuit (TCC), the processor, without the aid of any additional software or hardware, can keep the processors' die temperature within factory specifications under typical real world operating conditions. Thermal Monitor thus allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications, instead of being designed to the much higher maximum theoretical processor power envelopes. Thermal Monitor controls the processor temperature by modulating the internal processor core clocks. The processor clocks are modulated when the TCC is activated. Thermal Monitor uses two modes to activate the TCC. Automatic mode and On-Demand mode. Automatic mode is required for the processor to operate within specifications and must first be enabled via BIOS. Once automatic mode is enabled, the TCC will activate only when the internal die temperature is very near the temperature limits of the processor. When TCC is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a a 50% duty cycle. Clocks will not be off more than 3 s when TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. Once the temperature has returned to a non-critical level, and the hysteresis timer has expired, modulation ceases and TCC goes inactive. Processor performance will be decreased by ~50% when the TCC is active (assuming a 50% duty cycle), however, with a properly designed and characterised thermal solution the TCC most likely will only be activated briefly when the system is near maximum temperature and during the most power intensive applications. For automatic mode, the 50% duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers or interrupt handling routines.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor Control Register is written to a "1" the TCC will be activated immediately, independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control Register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used at the same time Automatic mode is enabled, however, if the system tries to enable the TCC via On-Demand mode at the same time automatic mode is enabled AND a high temperature condition exists, the 50% duty cycle of the automatic mode will override the duty cycle selected by the On-Demand mode. An external signal, PROCHOT# (processor hot) is asserted any time the TCC is active (either in Automatic or On-Demand mode). Bus snooping and interrupt latching are also active while the TCC is active. The temperature at which the thermal control circuit activates is not user configurable and is not software visible. Besides the thermal sensor and thermal control circuit, the Thermal Monitor feature also includes one ACPI register, one performance counter register, three model specific registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Thermal Monitor feature. Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT# (i.e. upon the activation/deactivation of TCC). If automatic mode is disabled the processor will be operating out of specification and cannot be guaranteed to provide reliable results. Regardless of enabling of the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 C. At this point the system bus signal THERMTRIP# will go active and stay active until the processor has cooled down and RESET# has been initiated. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.
7.3.1
Thermal Diode
The Pentium 4 processor incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the Pentium 4 processor for thermal management/long term die temperature change purposes. Table 35 and Table 36 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.
Table 35. Thermal Diode Parameters
Symbol Iforward bias n_ideality Min 5 0.9933 1.0045 Typ Max 450 1.0368 Unit uA 2 3, 4 Notes1
NOTES: 1. Not 100% tested. Specified by design characterization. 2. Intel does not support or recommend operation of the thermal diode under reverse bias. 3. At room temperature with a forward bias of 630 mV. 4. n_ideality is the diode ideality factor parameter, as represented by the diode equation: I=Io(e (Vd*q)/(nkT) - 1).
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Table 36. Thermal Diode Interface
Pin Name THERMDA THERMDC Pin Number H38 E39 Pin Description diode anode diode cathode
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
8.0
8.1
Boxed Processor Specifications
Introduction
The Intel(R) Pentium(R) 4 Processor in the 423-pin Package is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from system boards and components. The boxed Pentium 4 processor will be supplied with a cooling solution. This chapter documents platform and system requirements for the cooling solution that will be supplied with the boxed Pentium 4 processor. This chapter is particularly important for OEMs that manufacture platforms for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and in inches [in brackets]. Figure 28 shows a mechanical representation of a boxed Pentium 4 processor.
*NOTE* Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designer's responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platform and chassis.
Figure 28. Mechanical Representation of the Boxed Pentium 4 Processor
Note:
The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
8.2
Mechanical Specifications
This section documents the mechanical specifications of the boxed Pentium 4 processor fan heatsink.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
8.2.1
Boxed Processor Fan Heatsink Dimensions
The boxed processor will be shipped with an unattached fan heatsink. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling (see Figure 33 and Figure 34). The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 29 (Side Views), and Figure 30 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new platform and system designs. Airspace requirements are shown in Figure 33 and Figure 34. Note that some figures have datum shown (marked with alphabetic designations) to clarify relative dimensioning.
Figure 29. Side View Space Requirements for the Boxed Processor
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 30. Top View Space Requirements for the Boxed Processor
8.2.2
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 3.0 and the Intel(R) Pentium(R) 4 Processor Thermal Design Guidelines for details on the processor weight and heatsink requirements. The boxed Pentium 4 processor requires direct-attach of the retention mechanism to the chassis wall, as described in the Intel Pentium 4 Processor ThermalMechanical Design Guide.
8.2.3
Boxed Processor Retention Mechanism and Fan Heatsink Supports
The boxed processor requires processor retention mechanisms to secure the processor in the baseboard socket. The boxed processor will not ship with retention mechanisms, or cooling solution retention clips. Platforms designed for use by system integrators should include retention mechanisms, and clips that support the boxed Pentium 4 processor. System board documentation should include appropriate retention mechanism installation instructions.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
8.3
8.3.1
Boxed Processor Requirements
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the system board. The power cable connector and pinout are shown in Figure 31. Platforms must provide a matched power header to support the boxed processor. Table 37 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open-collector output that pulses at a rate of two pulses per fan revolution. A system board pull-up resistor provides VOH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 32 shows the location of the fan power connector relative to the processor socket. The system board power header should be positioned within 4.33 inches from the center of the processor socket.
Figure 31. Boxed Processor Fan Heatsink Power Cable Connector Description
Table 37. Fan Heatsink Power and Signal Specifications
Description +12V: 12 volt fan power supply IC: Fan current draw SENSE: SENSE frequency NOTE: 1. System board should pull this pin up to VCC with a resistor. 2 Min 10.2 Typ 12 Max 13.8 300 V mA pulses/ rev 1 Unit Notes
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 32. Acceptable System Board Power Header Placement Relative to Processor Socket
8.4
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor.
8.4.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is found in Chapter 6.0 of this document. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 33) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 33 and Figure 34 illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 40C. Again, meeting the processor's temperature specification is the responsibility of the system integrator.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
Figure 33. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)
Figure 34. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
8.4.2
Variable Speed Fan
The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the upper set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains below the lower set point. These set points, represented in Figure 35 and Table 38, can vary by a few degrees from fan heatsink to fan heatsink.
Figure 35. Boxed Processor Fan Heatsink Set Points
Table 38. Boxed Processor Fan Heatsink Set Points
Boxed Processor Fan Heatsink Set Point (C) Boxed Processor Fan Speed When the internal chassis temperature is below this set point the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. When the internal chassis temperature is at this point the fan operates between its lowest and highest speeds. Recommended maximum internal chassis temperature for worst case operating environment. When the internal chassis temperature is above this set point the fan operates at its highest speed.
36
40
45 NOTES: 1. Set points may vary 1C.
The internal chassis temperature should be kept below 40C. When the internal chassis temperature increases above 45C, the Thermal Monitor may become active (see Section 7.3). Meeting the processor's temperature specification (see Chapter 6.0) is the responsibility of the system integrator.
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
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Intel(R) Pentium(R) 4 Processor in the 423-pin Package
9.0
9.1
Debug Tools Specifications
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Pentium 4 processor systems. Tektronix* and Agilent* should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Pentium 4 processor systems, the LAI is critical in providing the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind when designing a Pentium 4 processor system that can make use of an LAI: mechanical and electrical.
9.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the Pentium 4 processor. The LAI pins plug into the socket, while the Pentium 4 processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the Pentium 4 processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may include space normally occupied by the Pentium 4 processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
9.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide.
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Numerics
423-Pin Socket...................................................7, 8, 31
C
Clock Control ............................................................ 75 CMOS ....................................................................... 21 Common Clock AC Specifications ........................... 22 Common Clock Valid Delay Timings....................... 27 COMP[1:0]# definition of........................................................ 64 Configuration Timings .............................................. 29 CPUID......................................................................... 9
A
A10#...........................................................................75 A15#...........................................................................75 A20M# .......................................................................16 definition of ........................................................63 A7#.............................................................................75 A9#.............................................................................75 Activity Factor ...........................................................42 ADSTB# ....................................................................24 ADSTB[1:0]# definition of ........................................................63 ADS# .........................................................................16 definition of ........................................................63 advanced dynamic execution .......................................7 advanced transfer cache ...............................................7 AGTL+.......................................................................18 APIC Cluster ID.........................................................75 AP[1:0]# definition of ........................................................63 Assisted GTL+.............................................................8 Asychronous signals ..................................................16 Async GTL+ ..................................................17, 21, 24 AutoHALT.............................................................7, 75 AutoHALT Powerdown State....................................75 A[12:11]#...................................................................75 A[35:3]# defintion of..........................................................63
D
DBI[3:0]# definition of........................................................ 65 DBSY# definition of........................................................ 65 DC Specifications...................................................... 18 Debug Tools .............................................................. 89 Decoupling Guidelines.............................................. 11 Deep Sleep............................................................. 7, 75 Deep Sleep State........................................................ 78 DEFER# definition of........................................................ 65 Differential Clock Specifications .............................. 22 differential clocking .................................................. 12 DP[3:0]# definition of........................................................ 65 DRDY# definition of........................................................ 66 DSTBN[3:0]# definition of........................................................ 66 DSTBP[3:0]# definition of........................................................ 66 D[63:0]# definition of........................................................ 65
B
BCLK.............................................................16, 22, 78 BCLK.See also System Bus Clock BCLK[1:0] definition of ........................................................63 BINIT#...........................................................75, 76, 77 definition of ........................................................64 BIST...........................................................................75 BNR# definition of ........................................................64 Boxed Processor ........................................................81 BPM[5;0]# definition of ........................................................64 BPRI# definition of ........................................................64 BR0# definition of ........................................................64 BR# ............................................................................75 Bus Frequency ...........................................................22 Bus Parking................................................................75 Bus Voltage Definitions.............................................21
E
Effective Series Resistance ....................................... 12 EMI Guidelines ........................................................... 9 ESR.See Effective Series Resistance execution trace cache .................................................. 7
F
Features ..................................................................... 75 FERR# definition of........................................................ 66
G
Ground Pins............................................................... 11 GTLREF.................................................................... 11 definition of........................................................ 66
91
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
H
HALT.........................................................................75 HALT/Grant Snoop State ..........................................77 HALT/Grant Snoop state...........................................77 HITM# definition of ........................................................66 HIT# definition of ........................................................66 hyper pipelined technology..........................................7
Overshoot Checker Tool ....................................... 9, 39
P
Package Mechanical Specifications .......................... 31 phase-locked loop...................................................... 77 Pin Assignments........................................................ 51 Pin Listing ................................................................. 51 Platform Design Guide................................................ 9 PLL.See phase-locked loop Power........................................................................... 7 power distribution ..................................................... 11 Power Pins................................................................. 11 Power-On Configuration........................................... 75 Power-On Reset ........................................................ 29 Processor core ............................................................. 8 processor socket .................................................. 12, 31 Processor storage temperature................................... 18 processor supply voltage ........................................... 18 PROCHOT# definition of........................................................ 67 PWRGOOD definition of........................................................ 68
I
IERR# definition of ........................................................66 IGNNE#.....................................................................16 definition of ........................................................66 IHS.See also Integrated heat spreader INIT# ...................................................................75, 77 definition of ........................................................67 Integrated heat spreader ...............................................8 integrated heat spreader .............................................71 Intel Architecture Software Developer's Manual ........9 Interposer .....................................................................8 inter-symbol interference...........................................39 IOQ depth ..................................................................75 ITP_CLK[1:0] definition of ........................................................67 I/O Buffer Models..................................................9, 39 I/O buffer models.......................................................22
R
rapid execution engine ................................................ 7 reference voltage ....................................................... 21 REQ[4:0]# definition of........................................................ 68 RESERVED pins ...................................................... 15 Reset Condition AC Specifications........................... 24 RESET#........................................................... 8, 75, 77 definition of........................................................ 68 Retention mechanism .................................................. 8 Ringback ................................................................... 39 RSP# definition of........................................................ 68 RS[2:0]# definition of........................................................ 68
L
LINT ....................................................................75, 77 LINT[1:0] definition of ........................................................67 LOCK# definition of ........................................................67 Logic Analyzer Interface ...........................................89 Low Power States ......................................................75
M
Maximum Ratings .....................................................18 MCERR# ...................................................................75 definition of ........................................................67
S
Signal Quality Specifications.................................... 39 SKTOCC# definition of........................................................ 68 Sleep...................................................................... 7, 75 Sleep State................................................................. 77 SLP#.................................................................... 77, 78 definition of........................................................ 68 SMI#.................................................................... 75, 77 definition of........................................................ 69 snoop transaction....................................................... 77 snoop transactions ..................................................... 78 Source Synchronous Strobe Timings............................................. 28, 29
N
NMI..............................................................................8 Normal State ..............................................................75
O
OLGA.See also Organic Land Grid Array Organic Land Grid Array.............................................8 Output tristate ............................................................75 overshoot....................................................................39
92
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
source synchronous....................................................16 Source Synchronous AC Specifications ....................23 SSE2.See also Streaming SIMD Extensions 2 Stop Clock State Machine..........................................76 Stop-Grant..............................................................7, 75 Stop-Grant State...................................................76, 77 Stop-Grant state .........................................................77 STPCLK#...................................................................76 definition of ........................................................69 Streaming SIMD Extensions 2 ....................................7 System Bus ....................................................11, 12, 16 Reset and Configuration Timings.......................28 System bus ...................................................................8 System Bus AC Specifications ..................................22 System Bus Clock ......................................................12 System Bus Specifications.........................................21
Thermal Specifications.............................................. 71 Measurements .................................................... 72 THERMDA definition of........................................................ 69 THERMDC definition of........................................................ 69 THERMTRIP# definition of........................................................ 69 Timings Test Reset........................................................... 30 TMS definition of........................................................ 69 TRDY# definition of........................................................ 69 TRST# definition of........................................................ 69
T
TAP Signals AC Specifications.................................25 TCC.See also thermal control circuit TCK definition of ........................................................69 TDI definition of ........................................................69 TDO definition of ........................................................69 Termination resistors .................................................21 TESTHI......................................................................15 TESTHI pins ..............................................................16 TESTHI[10:0] definition of ........................................................69 Thermal Analysis.......................................................72 thermal control circuit................................................78 Thermal Design Guidelines .........................................9 Thermal Design Power ..............................................72 Thermal Diode ...........................................................79 Parameters...........................................................79 Thermal Monitor........................................7, 72, 78, 79 Thermal Power...........................................................72 Thermal Solution Locations for Case Temperature.........................73 thermal solution .........................................................71
U
undershoot ................................................................. 39
V
VCC........................................................................... 15 VccA definition of........................................................ 69 VccIOPLL definition of........................................................ 69 Vccsense definition of........................................................ 69 VID.See voltage identification VID[4:0] definition of........................................................ 70 Voltage Identification................................................ 12 Voltage Regulator Module .................................... 9, 12 VRM.See also Voltage Regulator Module VRM.See Voltage Regulator Module VSS ........................................................................... 15 VssA definition of........................................................ 70 Vsssense definition of........................................................ 70
93
Intel(R) Pentium(R) 4 Processor in the 423-pin Package
94

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